The present invention relates generally to integrated circuit (IC) design, and, more particularly, to an electrostatic discharge (ESD) trigger circuit design.
Static electricity exists on the surfaces of many materials. When bodies of different potential come into contact, electrostatic discharge (ESD) will occur. In semiconductor devices, such ESD can change the electrical characteristics of a semiconductor device, degrading or destroying them. Therefore, semiconductor devices all have ESD protection circuits on their bonding pads. Such ESD protection circuits, essentially, comprise a large discharge path triggered open only by an excessive potential, i.e., an electrostatic discharge event.
FIG. 1 illustrates a conventional ESD protection circuit 100 which comprises a voltage sensing circuit 110, an inverter 123, and an ESD protection device 130. The voltage sensing circuit 110 is comprised of a resistor 112 and a capacitor 114 that are serially connected between a bonding pad 102 under protection and a ground VSS. The capacitor 114 is implemented by a NMOS transistor with a source and a drain tied together to the VSS. The ESD protection device 130 is a large NMOS transistor with a source and a drain connected to the bonding pad 102 and the VSS, respectively. Large NMOS transistors being used for the ESD protection is because substantial amount of current needs to be dumped through the ESD protection device during an ESD event. A gate of the NMOS transistor 130 is connected to an output of the inverter 123 at a node N2. It is well known in the art that a potential between two terminals of a capacitor can not be changed instantly. When a logic high voltage is applied at the bonding pad 102, the voltage at a node N1 between the resistor 112 and the capacitor 114 ramps up from the VSS to the logic high voltage with a ramping rate depending on the values of the resistor 112 and capacitor 114. The inverter 123 serves merely as a voltage converting circuit, and particularly in this case, converts a logic low voltage at the node N1 to a logic high voltage at the node N2, and vice versa. With the initial logic low voltage at the node N1, hence the logic high voltage at the node N2, the NMOS transistor 130 is turned on, which drains off majority of the charge present at the bonding pad 102, therefore internal circuitries connected to the bonding pad 102 can be protected. As time goes by, the capacitor 114 is charged up with the voltage at the node N1 exceeds a threshold voltage of the inverter 123 and turns the voltage at the node N2 into a logic low voltage which turns off the NMOS transistor 130. Thereby, in a normal operation, the ESD protection circuit 130 does not interfere with normal functions of the bonding pad 102.
However, since the capacitor 114 has leakages through the gate oxide of the NMOS transistor, the voltage at the node N1 may not be high enough in a normal operation to completely turn off the NMOS transistor 130. It is undesirable for the ESD protection device 130 to consume current during the normal operation. To alleviate this gate oxide leakage problem, the capacitor 114 may use a thicker gate oxide. However, the thicker gate oxide with the constraint of the gate area decreases the capacitance of the capacitor 114. When the capacitor 114 is charged up too quickly, the turned-on period of the ESD protection device 130 will be shorter, thus the ESD protection circuit 100 will be less effective.
As such, what is desired is an ESD protection trigger circuit that can completely shut off the ESD protection device during a normal operation.